`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/01/03 16:00:02
// Design Name: 
// Module Name: mul
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mul(
    input clk,
    input wire[31:0] a,
    input wire[31:0] b,
    input wire [1:0]control,
    output wire[31:0] hi,
    output wire[31:0] lo,
    output wire mul_stall
    //output wire stall
);

    reg [3:0]star; //3: ce_un, 2: sclr_un, 1: ce_sign 1: sclr_sign
    wire [31:0] unsign_hi,unsign_lo,sign_hi,sign_lo;
    
    
    unsign_mult unsignmult(clk, a, b, 1, star[2], {unsign_hi,unsign_lo});
    sign_mult signmult(clk,a,b, 1, star[0],{sign_hi,sign_lo});
    always @(*)begin
        star<= 4'b0101;
        case(control)
            2'b10: star<= 4'b1001; 
            2'b11: star<= 4'b0110; 
            default: star<=4'b0101;
        endcase
    end
    assign hi=control[1]? control[0]? sign_hi:unsign_hi
                            :32'b0;
    assign lo=control[1]? control[0]? sign_lo:unsign_lo
                            :32'b0;
    //assign stall = control[1]? 1'b1:1'b0;

endmodule

//module div(
//    input wire[31:0] a,
//    input wire[31:0] b,
//    input wire is_sign,
//    input wire star,
//    output wire[31:0] hi,
//    output wire[31:0] lo
//);
//    assign hi=32'b0;
//    assign lo=32'b0;
    
//endmodule
